Genetic programming in hardware

Genetic Programming in Hardware This thesis describes a hardware implementation of a complete Genetic Programming (GP) system using a Field Programmable Gate Array, which is shown to speed-up GP by over 400 times when compared with a software implementation of the same algorithm. The hardware implements the creation of the initial population, breeding operators, parallel fitness evaluations and the output of the final result. The research was motivated by the observation that GP is usually implemented in software and run on general purpose computers. Although software implementations are flexible and easy to modify, they limit the performance of GP thus restricting the range of problems that GP can solve. The hypothesis is that implementing GP in hardware would speed up GP, allowing it to tackle problems which are currently too hard for software based GP. FPGAs are usually programmed using specialised hardware design languages. An alternative approach is used in this work that uses a high level language to hardware compilation system, called Handel-C. As part of this research, a number of general GP issues are also explored. The parameters of GP are described and arranged into a taxonomy of GP attributes. The taxonomy allows GP problems to be categorised with respect to their problem and GP specific attributes. The role that the GP algorithm plays in problem solving is shown to be part of a larger process called Meta-GP, which describes the overall process of developing a GP system and evolving a viable set of parameters to allow GP to solve a problem. Three crossover operators are investigated and a new operator, called single child limiting crossover, is presented. This operator appears to limit the tendency of GP to suffer from bloat. The economics of implementing GP in hardware are analysed and the costs and benefits are quantified. The thesis concludes by suggesting some applications for hardware GP.